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Low-latency scheduling in large switches
Author(s) -
Wladek Olesinski,
Nils Gura,
Hans Eberle,
Andrés Mejı́a
Publication year - 2007
Publication title -
citeseer x (the pennsylvania state university)
Language(s) - English
Resource type - Conference proceedings
DOI - 10.1145/1323548.1323566
Subject(s) - terabit , computer science , arbiter , gigabit , scheduling (production processes) , latency (audio) , computer network , embedded system , wavelength division multiplexing , telecommunications , engineering , operations management , wavelength , physics , optoelectronics
Scheduling in large switches is challenging. Arbiters must operate at high rates to keep up with the high switching rates demanded by multi-gigabit-per-second link rates and short cells. Low-latency requirements of some applications also challenge the design of schedulers. In this paper, we propose the Parallel Wrapped Wave Front Arbiter with Fast Scheduler (PWWFA-FS). We analyze its performance, present simulation results, discuss its implementation, and show how this scheme can provide low latency under light load while scaling to large switches with multi-terabit-per-second throughput and hundreds of ports.

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