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An integer programming (IP) model, which simultaneouslyschedules and allocates functional units, registers, and busses, ispresented for synthesizing cost-constrained globally optimalarchitectures. This research is important for industry by providingoptimal schedules which minimize interconnect costs and interfaceto analog and asynchronous processes, since these are seen as keyto synthesizing high performance architectures. A partiallystructured tight IP formulation of the architectural synthesisproblem provides globally optimal schedules for peicewise linearcost functions, using branch and bound, in execution times fasterthan previous research. This research breaks new ground by 1.simultaneously scheduling and allocating hardware resourcesincluding interconnect, 2. support for asynchronous and analoginterfaces, and 3. guaranteeing globally optimal solutions inpractical execution times.

Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis