Open AccessIn-lecture hardware demonstrations with a logic analyzer to illustrate pipelined execution and cache/memory behavior
Author(s) -
Naraig Manjikian
Publication year - 2000
Publication title -
citeseer x (the pennsylvania state university)
Language(s) - English
Resource type - Conference proceedings
DOI - 10.1145/1275240.1275260
Subject(s) - computer science , memory hierarchy , computer architecture , cache , spectrum analyzer , hierarchy , computer hardware , parallel computing , embedded system , telecommunications , economics , market economy
This paper describes the use of a logic analyzer for in-lecture demonstrations of pipelining and memory hierarchy on representative hardware. The aim is to enhance understanding of fundamental concepts without excessive technical detail. The hardware used in demonstrations is described along with the examples used and their pedagogical aims. Student feedback on this approach is also presented.
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