z-logo
open-access-imgOpen Access
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs
Author(s) -
Shunitsu Kohara,
Naoki Tomono,
Jumpei Uchida,
Yuichiro Miyaoka,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki
Publication year - 2006
Publication title -
waseda university repository (waseda university)
Language(s) - English
Resource type - Conference proceedings
ISBN - 0-7803-9451-8
DOI - 10.1145/1118299.1118440
Subject(s) - computer science , interface (matter) , system on a chip , multi core processor , core (optical fiber) , embedded system , computer architecture , integrated circuit design , parallel computing , telecommunications , bubble , maximum bubble pressure method
In SoC designs, efficient communication between the hardware IPs and the on-chip processor becomes very important, however the interface is usually affacted by the processor core specification. Thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores. we also propose a method to synthesize it. Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application.

The content you want is available to Zendy users.

Already have an account? Click here to sign in.
Having issues? You can contact us here
Accelerating Research

Address

John Eccles House
Robert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom