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Increasing levels of process variation in current process technologies make it extremely important that design and process decisions be made while considering their impact. This work presents a convex optimization based approach to select supply and threshold voltages to minimize power dissipation in generic multi-Vdd/Vth CMOS designs while considering process variation. We use this probabilistic approach to compare the optimization of different statistical parameters of power dissipation (e.g., mean or high percentile points), and quantify the impact of rising process variations on these power minimization techniques.

A general framework for probabilistic low-power design space exploration considering process variation