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We propose an integrated architectural/physical-planning approach named priority assignment optimization to minimize the current surge in high performance power efficient clock-gated microprocessors. The proposed approach balances the current demands across the floorplan by assigning optimized priorities to the functional units (FUs). Two complementary methods -- physical planning with soft modules and issue pattern management - to enhance our proposed approach are also discussed for various applications. Experimental results show that the proposed approach reduces the peak noise by 11.75% and consequently, the decoupling capacitance (Decap) requirement by 24.22% without any degradation in IPC (Instruction Per Cycle). We also show that our approach does not increase the clock period for the 0.18μm technology and beyond.

Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor