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We designed a compact, high-speed, and low-power bank-type 12-port register file test chip for highly-parallel processor in 0.35μm CMOS technology. In this full-custom test chip design, 72% smaller area, 25% shorter access cycle time, and 62% lower power consumption are achieved in comparison to the conventional 12-port-cell-based register file.

Compact 12-port multi-bank register file test-chip in 0.35/spl mu/m CMOS for highly parallel processors