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This paper presents the effects of SoC design with C language-based behavioral synthesis and verification. Initially, the proposed C-based design environment for a large SOC consisting of a hardware and embedded software is explained. Next, the increasse of design productivity by shifting from RTL to behavioral design will be discussed with statistical analysis of several industrial designs. Then, several merits of C-based design are examined using actual chip design results.

C-based behavioral synthesis and verification analysis on industrial design examples