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The rapid decrease in feature sizes has increasingly accentuated the importance of matching between transistors. Deep submicron designs will further emphasize the need to focus on the effects of mismatch. Furthermore, increased efforts on high level analog device modeling will necessitate accompanying mismatch simulation and measurement methods. The deep submicron era forces circuit designers to learn more about the physics and the technology of transistors. We introduce a method and assist circuit designers in including this method in their traditional design flow of circuits. By proposing a solution to the problem of building a modeling bridge between transistor mismatch and circuit response to it, we hope to enable designers to incorporate low level mismatch information in their higher level design.

On mismatch in the deep sub-micron era-from physics to circuits