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We investigate the impact of varying the grain boundary (GB) position on the output (Id–Vd) characteristics of submicron single GB polysilicon thin film transistors (TFTs), by two-dimensional (2D), drift-diffusion based, device simulation. We employ a localized GB trapping model with a distribution of both donor-like and acceptor-like trap states over the forbidden energy gap of the GB region. We show that for devices with channel lengths in the deep submicron regime, significant variations in output conductance (gd) occur as the GB position is varied. Specifically, we find that output conductance increases as the GB approaches the drain edge. Furthermore, the sensitivity of output conductance to the GB position increases as channel length decreases. The findings have important implications for any future analogue three-dimensional (3D) IC design that uses polysilicon as a device material.

Simulation Study of the Dependence of Submicron Polysilicon Thin-Film Transistor Output Characteristics on Grain Boundary Position