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Number-theoretic transforms (NTTs) have been applied in the fragilewatermarking of digital images. A block-parallel systolic-array architecture isproposed for watermarking based on the 2-D special Hartley NTT (HNTT). Theproposed core employs two 2-D special HNTT hardware cores, each using digitalarithmetic over $\mathrm{GF}(3)$, and processes $4\times4$ blocks of pixels inparallel every clock cycle. Prototypes are operational on a Xilinx Sx35-10ff668FPGA device. The maximum estimated throughput of the FPGA circuit is 100million $4\times4$ HNTT fragile watermarked blocks per second, when clocked at100 MHz. Potential applications exist in high-traffic back-end servers dealingwith large amounts of protected digital images requiring authentication, inremote-sensing for high-security surveillance applications, in real-time videoprocessing of information of a sensitive nature or matters of nationalsecurity, in video/photographic content management of corporate clients, inauthenticating multimedia for the entertainment industry, in the authenticationof electronic evidence material, and in real-time news streaming.

Block-Parallel Systolic-Array Architecture for 2-D NTT-based Fragile Watermark Embedding