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L. Parrilla, E. Castillo, U. Meyer-Bäse, A. García, D. González, E. Todorovich, E. Boemo, A. Lloris, "Watermarking strategies for IP protection of micro-processor cores", Proceedings of SPIE 7703, Independent Component Analyses, Wavelets, Neural Networks, Biosystems, and Nanoengineering VIII, 77030L (2010). Copyright 2010 Society of Photo‑Optical Instrumentation Engineers. One print or electronic copy may be made for personal use only. Systematic reproduction and distribution, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited.Reuse-based design has emerged as one of the most important methodologies for integrated circuit design, with reusable Intellectual Property (IP) cores enabling the optimization of company resources due to reduced development time and costs. This is of special interest in the Field-Programmable Logic (FPL) domain, which mainly relies on automatic synthesis tools. However, this design methodology has brought to light the intellectual property protection (IPP) of those modules, with most forms of protection in the EDA industry being difficult to translate to this domain. However, IP core watermarking has emerged as a tool for IP core protection. Although watermarks may be inserted at different levels of the design flow, watermarking Hardware Description Language (HDL) descriptions has been proved to be a robust and secure option. In this paper, a new framework for the protection of μP cores is presented. The protection scheme is derived from the IPP@HDL procedure and it has been adapted to the singularities of μP cores, overcoming the problems for the digital signature extraction in such systems. Additionally, the feature of hardware activation has been introduced, allowing the distribution of μP cores in a "demo" mode and a later activation that can be easily performed by the customer executing a simple program. Application examples show that the additional hardware introduced for protection and/or activation has no effect over the performance, and showing an assumable area increase.This work was partially funded by project TEC2007-68074-C02-01/MIC (Plan Nacional I+D+I, Spain). CAD tools andsupporting material were provided by Altera Corp. trough University Program agreements. Any opinions, findings, andconclusions or recommendations expressed in this paper are those of the authors and do not necessarily reflect the viewsof the sponsors