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Dummy ll insertion in Chemical-mechanical Planarization (CMP) can change the coupling and total capaci-tance of interconnect. Moreover, dishing and erosion phenomena change interconnect cross-sections and hence signi cantly a ect interconnect resistance. This work rst studies interconnect parasitic variations due to i. di erent ll patterns that are nominally \equivalent" with respect to foundry rules; and ii. dishing and erosion of conductors and dielectric using an accurate density-step-height model for multi-step CMP from the literature. Our results show that for long parallel wires the variation of coupling capacitance between adjacent wires can be up to 25% and 300% for wires that are 3x and 6x minimum-space apart respectively, and the variation of total wire capacitance can be as large as 10%. We also show that the variation of wire resistance due to dishing and erosion can be over 30%. This work also evaluates how CMP e ects ( ll insertion, dishing and erosion) impact the achievable delay of bu ered global on-chip interconnects. We obtain the delay of buses from accurate SPICE simulations considering CMP-related parasitic variation. Our studies show that in the regime of best-possible ll pattern solutions, CMP-aware design reduces delay per length of global interconnect bus by up to 3.3%. We also show that no single design is CMP-variation optimized.

Design of integrated-circuit interconnects with accurate modeling of chemical-mechanical planarization