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In recent years, CCD-in-CMOS TDI image sensors are becoming increasinglypopular for many small satellite missions to assure a fast and affordableaccess to space for Low Earth Observation. Our monolithic CCD-in-CMOS TDIimager features a specifically developed technology which combines the benefitsof a classical CCD TDI with the advantages of CMOS System-On-a-Chip (SoC)design. Like CCD, this detector is also controlled by a large number of clockvoltages. Optimizing these voltages allows to increase the performance of thedetector by improving multiple characteristic parameters, such as full wellcapacity (FWC), dark current, linearity, dark signal non-uniformity (DSNU) andcharge transfer efficiency (CTE). Traditionally, it has been the standardpractice to adjust the CCD voltages by trial and error methods to get a betterimage. Because of the large parameter space, such subjective procedures mayyield far from the optimum performance. This paper reports a design ofexperiments (DOE) technique applied on the clock voltages to improve themultiple performance parameters of the detector. This method utilizes theTaguchi's orthogonal arrays of experiments to reduce the number of experimentswith different voltage combinations. Finally, optimal combination of clockvoltages is obtained by converting the multiple performance parameters of thedetector into a single Grey relational grade. In this process, the sequences ofobtaining parameter values are categorized according to the performancecharacteristics. The condition Higher-the-better is used for parameters likeFWC and CTE whereas condition Lower-the-better is applied for parameters, suchas dark current, linearity error and DSNU.

Optimization of a CCD-in-CMOS TDI detector's operating clock voltages by Taguchi based Grey relational analysis