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Three-dimensional integration of stacked device cells in front end (FE) and of advanced metallization in back end (BE) enabled by through-silicon via (TSV) opens new paths to increased product functionality even without device shrink. But “going 3-D” also creates many new challenges for the semiconductor industry. Development of the new designs, manufacturing methods, and processes demands rapid technology and materials characterization, as well as in-line metrology and inspection for process development and control in completely new and changing applications environments.

Special Section Guest Editorial: Metrology and Inspection for 3-D Integrated Circuits and Interconnects