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In semiconductor wafer fabs, hot lots refer to a group of products which have high priority for various reasons, e.g, pilot products or due date commitments to customers. Hot lots are given the highest priority with the purpose of reducing their cycle time. However, hot lots often cause irregular WIP flow that has great impact on cycle time and throughput of regular lots. In this paper, we present a simulation study including two cases on handling degraded performance of regular lots under the control of minimum inventory variability scheduling (MIVS) and operation due date (ODD). In the first case, when hot lots represent 10% of total release, we propose to improve the pace of lot movement for MIVS and break dominance of due date control ODD. In the second case, as the percentage of hot lots increases to 30%, we apply a hierarchical dispatching scheme in which target cycle time is set higher for hot lots and regular lots. The simulation results show that for the first case, the compensatory methods are able to improve the performance of regular lots by overcoming deficiencies of MIVS and ODD; for the second case, it is important to establish a target cycle time if a trade-off is needed between hot lots and regular lots.

A Simulation Study on the Performance of Wafer Fabs with Hot Lots Under WIP Balance and Due Date Control Policies