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A new silicon-strip readout chip named &#x201C;SliT&#x201D; has been developed for the measurement of the muon anomalous magnetic moment and electric dipole moment (EDM) of the muon at Japan Proton Accelerator Research Complex (J-PARC). The SliT chip is designed in the Silterra 180-nm CMOS technology with mixed-signal integrated circuits. An analog circuit incorporates a conventional charge-sensitive amplifier, shaping amplifiers, and two distinct discriminators for each of the 128 identical channels. A digital part includes storage memories, an event building block, a serializer, and low voltage differential signaling (LVDS) drivers. A distinct feature of the SliT is utilization of the zero-crossing architecture, which consists of a CR-RC filter followed by a CR circuit as a voltage differentiator. This architecture allows generating hit signals with subnanosecond amplitude-independent time walk, which is the primary requirement for the experiment. The test results show a time walk of 0.38 &#x00B1; 0.16 ns between 0.5 and 3 MIP signals. The equivalent noise charge is 1547 &#x00B1; 75 e<sup>-</sup> (rms) at C<sub>det</sub> = 33 pF as a strip-sensor capacitance. SliT128C satisfies all requirements of the J-PARC muon g - 2/EDM experiment.

SliT: A Strip-Sensor Readout Chip With Subnanosecond Time Walk for the J-PARC Muon g − 2/EDM Experiment