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Clock synchronization procedures are mandatory in most physical experimentswhere event fragments are readout by spatially dislocated sensors and must beglued together to reconstruct key parameters (e.g. energy, interaction vertexetc.) of the process under investigation. These distributed data readouttopologies rely on an accurate time information available at the frontend,where raw data are acquired and tagged with a precise timestamp prior to databuffering and central data collecting. This makes the network complexity andlatency, between frontend and backend electronics, negligible within upperbounds imposed by the frontend data buffer capability. The proposed researchwork describes an FPGA implementation of IEEE 1588 Precision Time Protocol(PTP) that exploits the CERN Timing, Trigger and Control (TTC) system as amulticast messaging physical and data link layer. The hardware implementationextends the clock synchronization to the nanoseconds range, overcoming thetypical accuracy limitations inferred by computers Ethernet based Local AreaNetwork (LAN). Establishing a reliable communication between master and timingreceiver nodes is essential in a message-based synchronization system. In thebackend electronics, the serial data streams synchronization with the globalclock domain is guaranteed by an hardware-based finite state machine that scansthe bit period using a variable delay chain and finds the optimal samplingpoint. The validity of the proposed timing system has been proved inpoint-to-point data links as well as in star topology configurations overstandard CAT-5e cables. The results achieved together with weaknesses andpossible improvements are hereby detailed.

Nanoseconds Timing System Based on IEEE 1588 FPGA Implementation