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We present an FPGA-based online data reduction system for the pixel detector of the future Belle II experiment. The occupancy of the pixel detector is estimated at 3%. This corresponds to a data output rate of more than 20 GB/s after zero suppression, dominated by background. The Online Selection Nodes (ONSEN) system aims to reduce the background data by a factor of 30. It consists of 33 MicroTCA cards, each equipped with a Xilinx Virtex-5 FPGA and 4 GiB DDR2 RAM. These cards are hosted by 9 AdvancedTCA carrier boards. The ONSEN system buffers the entire output data from the pixel detector for up to 5 seconds. During this time, the Belle II high-level trigger PC farm performs an online event reconstruction, using data from the other Belle II subdetectors. It extrapolates reconstructed tracks to the layers of the pixel detector and defines regions of interest around the intercepts. Based on this information, the ONSEN system discards all pixels not inside a region of interest before sending the remaining hits to the event builder system. During a beam test with one layer of the pixel detector and four layers of the surrounding silicon strip detector, including a scaled-down version of the high-level trigger and data acquisition system, the pixel data reduction using regions of interest was exercised. We investigated the data produced in more than 20 million events and verified that the ONSEN system behaved correctly, forwarding all pixels inside regions of interest and discarding the rest.

The ONSEN Data Reduction System for the Belle II Pixel Detector