English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools annual

Global: Zendy Free Plan

Global: Zendy Tools monthly

Global: Zendy Plus monthly

We investigate the charge trapping during endurance fatigue of FeFET with TiN/Hf0.5Zr0.5O2/SiO2/Si (MFIS) gate structure. We propose a method of experimentally extracting the number of trapped charges during the memory operation, by measuring the charges in the metal gate and Si substrate. We verify that the amount of trapped charges increases during the endurance fatigue process. This is the first time that the trapped charges are directly experimentally extracted and verified to increase during endurance fatigue. Moreover, we model the interplay between the trapped charges and ferroelectric polarization switching during endurance fatigue. Through the consistency of experimental results and simulated data, we demonstrate that as the memory window (MW) decreases: 1) the ferroelectric characteristic of Hf0.5Zr0.5O2 is not degraded; 2) the trap density in the upper bandgap of the gate stacks increases; and 3) the reason for MW decrease is increased trapped electrons after program operation but not related to hole trapping/detrapping. Our work is helpful to study the charge trapping behavior of FeFET and the related endurance fatigue process.

Experimental Extraction and Simulation of Charge Trapping During Endurance of FeFET With TiN/HfZrO/SiO2/Si (MFIS) Gate Structure

Experimental Extraction and Simulation of Charge Trapping During Endurance of FeFET With TiN/HfZrO/SiO₂/Si (MFIS) Gate Structure