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Quantification of interface traps for double-gate fully depleted silicon-on-insulator transistors is needed for accurate device modeling and technology development. The trap density can be estimated as a function of the activation energy from the subthreshold current using the methodology developed in this work. It combines the earlier proposed <inline-formula> <tex-math notation="LaTeX">${g}_{\text {m}}/ {I}_{\text {D}}$ </tex-math></inline-formula> method with a revised form of the <inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula>-sweep method. The method is verified using TCAD simulated data and applied on engineering samples produced in 22FDX (R) technology, yielding a typical trap density of <inline-formula> <tex-math notation="LaTeX">${2}\,\,\cdot \,\,{10}^{{11}}\,\,\text {cm}^{-{2}}\text {eV}^{-{1}}$ </tex-math></inline-formula>. Association of the traps to the front or back interface is nontrivial; a trap allocation error of at least 20&#x0025; is reported.

Interface States Characterization of UTB SOI MOSFETs From the Subthreshold Current