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This paper presents a compact model for P<sup>+</sup> guard rings in lightly doped CMOS substrates featuring a P-well layer. Simple expressions for the impedances in the model are derived based on a conformal mapping approach. The model can be used to predict the noise suppression performance of P<sup>+</sup> guard rings in terms of S-parameters, which is useful for substrate noise mitigation in mixed-signal system-on-chips. Validation of the model has been done by both electromagnetic simulation and experimental results from guard rings implemented using a standard 0.18- &#x03BC;m CMOS process. In addition, design guidelines have been drawn for minimizing the guard ring size while maintaining the noise suppression performance.

ieee transactions on electron devices

Modeling and Design Guidelines for <formula formulatype="inline"><tex Notation="TeX">${\rm P}^{+}$</tex></formula> Guard Rings in Lightly Doped CMOS Substrates

Modeling and Design Guidelines for ${\rm P}^{+}$ Guard Rings in Lightly Doped CMOS Substrates