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In this brief, we show how to derive all the optimum multi-path delay commutator (MDC) fast Fourier transform (FFT) hardware architectures in terms of delays and multiplexers and calculate the number of such architectures. The proposed approach is based on analyzing the orders at the FFT stages that lead to optimum number of delays and multiplexers. The results show that there exist a large number of optimum MDC FFTs. This large design space can be explored in the future in order to design efficient MDC architectures that not only optimize the number of delays and multiplexers, but also other figures of merit such as the number of rotators or the input/output data order.

Optimum MDC FFT Hardware Architectures in Terms of Delays and Multiplexers