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This article presents a wide-band suppression technique of flicker phase noise (PN) by means of a gate&#x2013;drain phase shift in a transformer-based complementary oscillator. We identify that after naturally canceling its second-harmonic voltage by the complementary operation itself, third-harmonic current entering the capacitive path is now the main cause of asymmetry in the rising and falling edges, leading to the <inline-formula> <tex-math notation="LaTeX">$1/f$ </tex-math></inline-formula> noise upconversion. A complete <inline-formula> <tex-math notation="LaTeX">$1/f^{3}$ </tex-math></inline-formula> PN analysis for the transformer-based complementary oscillator is discussed. By tuning gate&#x2013;drain capacitance ratio, a specific phase-shift <italic>range</italic> is introduced at the gate and drain nodes of the cross-coupled pair to mitigate the detrimental effects of ill-behaved third-harmonic voltage, thus lowering the flicker PN. To further reduce the area and improve the PN in the thermal region, we introduce a new triple-8-shaped transformer. Fabricated in 22-nm FDSOI, the prototype occupies a compact area of 0.01mm<sup>2</sup> and achieves <inline-formula> <tex-math notation="LaTeX">$1/f^{3}$ </tex-math></inline-formula> PN corner of 70kHz, PN of &#x2212;110dBc/Hz at 1MHz offset, figure-of-merit (FoM) of &#x2212;182dB at 9GHz, and 39&#x0025; tuning range (TR). It results in the best FoM with normalized TR and area (FoM<sub>TA</sub>) of &#x2212;214dB at 1MHz offset.

Flicker Phase-Noise Reduction Using Gate–Drain Phase Shift in Transformer-Based Oscillators