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The proliferation of high-throughput sequencing machines ensures rapid generation of up to billions of short nucleotide fragments in a short period of time. This massive amount of sequence data can quickly overwhelm today&#x0027;s storage and compute infrastructure. This paper explores the use of hardware acceleration to significantly improve the runtime of short-read alignment, a crucial step in preprocessing sequenced genomes. We focus on the Levenshtein distance (edit-distance) computation kernel and propose the ASAP accelerator, which utilizes the intrinsic delay of circuits for edit-distance computation elements as a proxy for computation. Our design is implemented on an Xilinx Virtex 7 FPGA in an IBM POWER8 system that uses the CAPI interface for cache coherence across the CPU and FPGA. Our design is <inline-formula><tex-math notation="LaTeX">$200\times$</tex-math><alternatives><inline-graphic xlink:href="banerjee-ieq1-2875733.gif"/></alternatives></inline-formula> faster than an equivalent Smith-Waterman-C implementation of the kernel running on the host processor, <inline-formula><tex-math notation="LaTeX">$40-60\times$</tex-math><alternatives><inline-graphic xlink:href="banerjee-ieq2-2875733.gif"/></alternatives></inline-formula> faster than an equivalent Landau-Vishkin-C++ implementation of the kernel running on the IBM Power8 host processor, and <inline-formula><tex-math notation="LaTeX">$2\times$</tex-math><alternatives><inline-graphic xlink:href="banerjee-ieq3-2875733.gif"/></alternatives></inline-formula> faster for an end-to-end alignment tool for 120&#x2013;150 base-pair short-read sequences. Further the design represents a <inline-formula><tex-math notation="LaTeX">$3760\times$</tex-math><alternatives><inline-graphic xlink:href="banerjee-ieq4-2875733.gif"/></alternatives></inline-formula> improvement over the CPU in performance/Watt terms.

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ASAP: <underline>A</underline>ccelerated <underline>S</underline>hort-Read <underline>A</underline>lignment on <underline>P</underline>rogrammable Hardware

ASAP: Accelerated Short-Read Alignment on Programmable Hardware