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Multiple cell upsets (MCUs) become more and more problematic as the size of technology reaches or goes below 65&#x00A0;nm. The percentage of MCUs is reported significantly larger than that of single cell upsets (SCUs) in 20&#x00A0;nm technology. In SRAM and DRAM, MCUs are tackled by incorporating single-error correcting double-error detecting (SEC-DED) code and interleaved data columns. However, in content-addressable memory (CAM), column interleaving is not practically possible. A novel error correction code (ECC) scheme is proposed in this paper that will cater for ever-increasing MCUs. This work demonstrated that m parity bits are sufficient to cater for up to m-bit MCUs, with an understanding of the physical grouping of MCUs. The results showed that the proposed scheme requires 85% fewer parity bits compared to traditional Hamming distance based schemes.

An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory