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Recent trends in the field of neural network accelerators investigate weightquantization as a means to increase the resource- and power-efficiency ofhardware devices. As full on-chip weight storage is necessary to avoid the highenergy cost of off-chip memory accesses, memory reduction requirements forweight storage pushed toward the use of binary weights, which were demonstratedto have a limited accuracy reduction on many applications whenquantization-aware training techniques are used. In parallel, spiking neuralnetwork (SNN) architectures are explored to further reduce power whenprocessing sparse event-based data streams, while on-chip spike-based onlinelearning appears as a key feature for applications constrained in power andresources during the training phase. However, designing power- andarea-efficient spiking neural networks still requires the development ofspecific techniques in order to leverage on-chip online learning on binaryweights without compromising the synapse density. In this work, we demonstrateMorphIC, a quad-core binary-weight digital neuromorphic processor embedding astochastic version of the spike-driven synaptic plasticity (S-SDSP) learningrule and a hierarchical routing fabric for large-scale chip interconnection.The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF)neurons and more than two million plastic synapses for an active silicon areaof 2.86mm$^2$ in 65nm CMOS, achieving a high density of 738k synapses/mm$^2$.MorphIC demonstrates an order-of-magnitude improvement in the area-accuracytradeoff on the MNIST classification task compared to previously-proposed SNNs,while having no penalty in the energy-accuracy tradeoff.

MorphIC: A 65-nm 738k-Synapse/mm$^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning