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We have designed and tested a parallel 8-bit ERSFQ binary shifter that is oneof the essential circuits in the design of the energy-efficient superconductingCPU. The binary shifter performs a bi-directional SHIFT instruction of an 8-bitargument. It consists of a bi-direction triple-port shift register controlledby two (left and right) shift pulse generators asynchronously generating a setnumber of shift pulses. At first clock cycle, an 8-bit word is loaded into thebinary shifter and a 3-bit shift argument is loaded into the desiredshift-pulse generator. Next, the generator produces the required number ofshift SFQ pulses (from 0 to 7) asynchronously, with a repetition rate set bythe internal generator delay of ~ 30 ps. These SFQ pulses are applied to theleft (positive) or the right (negative) input of the binary shifter. Finally,after the shift operation is completed, the resulting 8-bit word goes to theparallel output. The complete 8-bit ERSFQ binary shifter, consisting of 820Josephson junctions, was simulated and optimized using PSCAN2. It wasfabricated in MIT Lincoln Lab 10-kA/cm2 SFQ5ee fabrication process with ahigh-kinetic inductance layer. We have successfully tested the binary shifterat both the LSB-to-MSB and MSB-to-LSB propagation regimes for all eight shiftarguments. A single shift operation on a single input word demonstratedoperational margins of +/-16% of the dc bias current. The correct functionalityof the 8-bit ERSFQ binary shifter with the large, exhaustive data pattern wasobserved within +/-10% margins of the dc bias current. In this paper, wedescribe the design and present the test results for the ERSFQ 8-bit parallelbinary shifter.

ERSFQ 8-bit Parallel Binary Shifter for Energy-Efficient Superconducting CPU