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We present our new fabrication Process for Superconductor Electronics (PSE2)that integrates two (2) layers of Josephson junctions in a fully planarizedmultilayer process on 200-mm wafers. The two junction layers can be, e.g.,conventional Superconductor-Insulator-Superconductor (SIS) Nb/Al/AlO_x/Nbjunctions with the same or different Josephson critical current densities, J_c.The process also allows integration of high-J_cSuperconductor-Ferromagnet-Superconductor (SFS) or SFS'S JJs on the firstjunction layer with Nb/Al/AlO_x/Nb trilayer junctions on the second junctionlayer, or vice versa. In the present node, the SFS trilayer, Nb/Ni/Nb is placedbelow the standard SIS trilayer and separated by one niobium wiring layer. Themain purpose of integrating the SFS and SIS junction layers is to providecompact {\pi}-phase shifters in logic cells of superconductor digital circuitsand random access memories, and thereby increase the integration scale andfunctional density of superconductor electronics. The current node of thetwo-junction-layer process has six planarized niobium layers, two layers ofresistors, and 350-nm minimum feature size. The target Josephson criticalcurrent densities for the SIS junctions are 100 {\mu}A/{\mu}m^2 and 200{\mu}A/{\mu}m^2. We present the salient features of the new process,fabrication details, and characterization results on two layers of Josephsonjunctions integrated into one process, both for the conventional and{\pi}-junctions.

Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS {\pi}-Junctions