*T: Integrated building blocks for parallel computing

The authors present two hardware components for high performance parallel computing: a superscalar RISC microprocessor with an integrated 400 Mb/s user-level network interface (the 88110MP), and a companion 8 × 8 low-latency packet router chip (ARTIC). The design point combines very low message overhead and high delivered communications bandwidth with a commercially competitive sequential processor core. The network interface is directly programmed in user mode as an instruction set extension to the Motorola 88110. Importantly, naming and protection mechanisms are provided to support robust multi-user space and time sharing. Thus, fine-grain messaging and synchronization can be supported efficiently, without compromising pre-processor performance or system integrity. Preliminary performance modeling results are presented.