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Since solar energy generation is getting more and more important worldwide PV systems and solar parks are becoming larger consisting of an increasing number of solar panels being serially interconnected. As a consequence panels are frequently exposed to high relative potentials towards ground causing High Voltage Stress (HVS). The effect of HVS on long term stability of solar panels depending on the leakage current between solar cells and ground has been first addressed by NREL in 2005 [1]. This potential degradation mechanism is not monitored by the typical PV tests listed in IEC 61215 [2]. Depending on the technology different types of Potential Induced Degradation (PID) occur. This paper is focusing on PID of wafer based standard p-type silicon technology aiming on increasing life times for solar panels once exposed to external potentials in the field. A test setup is presented for simulation of the PID in the lab and the influence of cell properties on PID is demonstrated in order to reveal the cell being the precondition for the PID. However, PID can also be stopped or minimized on panel and system level as shown in the paper.

Potential Induced Degradation of solar cells and panels