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In-band full-duplex (IBFD) is an attractive solution for increasing the throughput of Power Line Communication (PLC) systems. In IBFD, each network node is allowed to transmit and receive simultaneously in the same frequency band. This paper discusses the importance of defining figures of merit to analyze IBFD performance, which is often forgotten by the literature that addresses IBFD from a pure system level and signal processing perspective. This is because in IBFD hardware-related aspects are of great importance. The focus is then given to the first self-interference (SI) cancellation stage, namely the analog coupling and self-interference cancellation stage (ASICS). Two architectures are considered. A detailed analysis is offered by taking into account circuit-level aspects. A broadband multiple conductor PLC scenario is assumed to enable multiple-input multiple-output (MIMO) IBFD communication. The first considered architecture performs SI subtraction exploiting operational amplifiers. The second proposed architecture exploits the characteristics of a three ports magnetic circuit together with a signal generator to remove the SI. Design, analysis, and hardware realization of these circuits have been done to compare and show the practical feasibility of the ASICS for PLC, well known to be challenged by its line impedance matching problems and severe frequency selective channel characteristics. This paper is the first documented contribution of the IBFD ASICS for 2&#x00D7;2 MIMO broadband PLC physically realized and tested in the field.

MIMO In-Band-Full-Duplex PLC: Design, Analysis and First Hardware Realization of the Analog Self-Interference Cancellation Stage