English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools annual

Global: Zendy Free Plan

Global: Zendy Tools monthly

Global: Zendy Plus monthly

Data protection is a severe constraint in the heterogeneous IoT era. This article presents a hardware–software cosimulation of AES-128 bit encryption and decryption for IoT edge devices using the Xilinx system generator. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) implementation of AES-128 bit algorithm is done with ECB and CTR modes using loop unrolled and finite-state machine (FSM) based architecture. It is found that AES-CTR and FSM architecture performance is better than loop unrolled architecture with lesser power consumption and area. For performing the hardware–software cosimulation on Zedboard and Kintex UltraScale KCU105 evaluation platform, Xilinx Vivado 2016.2 and MATLAB 2015b are used. Hardware emulation is done for grey images successfully. To give a practical example of the usage of proposed framework, we have applied it for biomedical images (CT scan image) as a case study. Security analysis in terms of the histogram, correlation, information entropy analysis, and keyspace analysis using exhaustive search and key sensitivity tests is also done to encrypt and decrypt images successfully.

Hardware–Software Co-Design Framework for Data Encryption in Image Processing Systems for the Internet of Things Environment