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Substrate coupling in 3-D-ICs using Cu through silicon vias (TSVs) is a predicament widely documented in recent literature. Yet, discussions remain limited to the electromagnetic framework, such that a complete understanding of noise propagation and absorption is hampered. This letter thoroughly examines these phenomena in the TSVs from the integrated perspectives of semiconductor physics and electromagnetic theory and investigates the noise reduction method using the combination of p+ guard-ring and grounded TSV via 3-D device simulation.

3-D Transient Analysis of TSV-Induced Substrate Noise: Improved Noise Reduction in 3-D-ICs With Incorporation of Guarding Structures