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CMOS single-photon avalanche diodes (SPADs) have broken into the mainstream by enabling the adoption of imaging, timing, and security technologies in a variety of applications within the consumer, medical and industrial domains. The continued scaling of technology nodes creates many benefits but also obstacles for SPAD-based systems. Maintaining and/or improving upon the high-sensitivity, low-noise, and timing performance of demonstrated SPADs in custom technologies or well-established CMOS image sensor processes remains a challenge. In this paper, we present SPADs based on DPW/BNW junctions in a standard Bipolar-CMOS-DMOS (BCD) technology with results comparable to the state-of-the-art in terms of sensitivity and noise in a deep sub-micron process. Technology CAD (TCAD) simulations demonstrate the improved PDP with the simple addition of a single existing implant, which allows for an engineered performance without modifications to the process. The result is an 8.8 <inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m diameter SPAD exhibiting <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula>2.6 cps/<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m<inline-formula><tex-math notation="LaTeX">$^2$</tex-math></inline-formula> DCR at 20 <inline-formula><tex-math notation="LaTeX">$^{\circ}$</tex-math></inline-formula>C with 7 V excess bias. The improved structure obtains a PDP of 62&#x0025; and <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula>4.2&#x0025; at 530 nm and 940 nm, respectively. Afterpulsing probability is <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula>0.97&#x0025; and the timing response is 52 ps FWHM when measured with integrated passive quench/active recharge circuitry at 3 V excess bias.

Engineering Breakdown Probability Profile for PDP and DCR Optimization in a SPAD Fabricated in a Standard 55 nm BCD Process