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In many applications, the ability of current references to cope with process, voltage, and temperature (PVT) variations is critical to maintaining system-level performance. However, temperature-independent current references operating in the nA range are rarely area-efficient due to the use of large resistors which occupy a significant silicon area at this current level. In this article, we introduce a nA-range constant-with-temperature (CWT) current reference relying on a self-cascode MOSFET (SCM), biased by a proportional-to-absolute-temperature (PTAT) voltage with a CWT offset. On the one hand, the proposed reference has been simulated post-layout in 65-nm bulk. This design consumes 5.4 nW at 0.7 V and achieves a 1.1-nA current with a line sensitivity (LS) of 0.69    $\%$   /V and a temperature coefficient (TC) of 213 ppm/   $^\circ$   C. On the other hand, the proposed reference has been simulated and fabricated in 22-nm fully depleted silicon-on-insulator (FDSOI). This second design requires additional features to mitigate the impact of parasitic diode leakage at high temperature. In measurement, it consumes 5.8 nW at 0.9 V and achieves a 0.9-nA current with a 0.39-   $\%$   /V LS and a 565-ppm/   $^\circ$   C TC. As a result of using an SCM, the proposed references occupy a silicon area of 0.0021 mm   $^2$    in 65 nm (respectively, 0.0132 mm   $^2$    in 22 nm) at least 25   $\times$    (respectively, 4   $\times$   ) smaller than state-of-the-art CWT references operating in the same current range.

A 1.1-/ 0.9-nA Temperature-Independent 213-/ 565-ppm/ $^\circ$ C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI