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We propose and demonstrate a new low-complexity hardware architecture and digital signal processing (DSP) implementation for coherent reception of Nyquist frequency division multiplexed (Nyquist-FDM, digital subcarrier multiplexing) signals in real time. Key to achieve lowest complexity is the combination of an optimized frequency domain and time domain processing block. In the frequency domain processing, we combine subcarrier equalization and timing recovery with a noninteger oversampling ratio of 16/15. In the time domain, we take advantage of polar coordinate processing for the carrier recovery to avoid complex multiplications. The receiver is optimized for flexible operation and allows the adaption of filter coefficients and modulation format between 4QAM, hybrid 4/16QAM, and 16QAM within one clock cycle. The efficiency of the DSP is demonstrated by a real-time coherent receiver implementation on a single FPGA and is experimentally evaluated. Despite of the limited hardware resources, the receiver can detect a 30 GBd Nyquist-FDM signal with four subcarriers and a net data rate of 60 Gb/s (4QAM), 90 Gb/s (4/16QAM), or 120 Gb/s (16QAM) sampled with 32 GSa/s and demodulate one of the subcarriers at a time. Transmission of 300 km through standard single mode fiber is demonstrated with a BER below the soft-decision forward error correction limit.

Low-Complexity Real-Time Receiver for Coherent Nyquist-FDM Signals