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Traditional in-Silicon PN-junction-based on-chip electrostatic discharge (ESD) protection structures have inherent ESD-induced design overhead problems, including parasitic capacitance, leakage and Si area consumption. A potential solution to the ESD design overhead challenge is to use a non-conventional above-Si graphene-based nano-electrical mechanical system (gNEMS) transient switch structure to protect integrated circuits (ICs) against ESD failures. This paper reports investigation of materials and device structural impacts on gNEMS ESD protection structures. Transmission-line pulse (TLP) testing confirms that single-crystalline graphene gNEMS switch achieves a record high ESD current-handling capability of <inline-formula> <tex-math notation="LaTeX">$\text{J}_{t2} {\mathbf {\sim }} 1.03\boldsymbol {\times } 10^{9}\text{A}$ </tex-math></inline-formula>/cm<sup>2</sup>, at least four times higher than <inline-formula> <tex-math notation="LaTeX">$\text{J}_{t2} {\mathbf {\sim }} 0.24\boldsymbol {\times } 10^{9}\text{A}$ </tex-math></inline-formula>/cm<sup>2</sup> for its poly-crystalline graphene counterpart. Transient 3D finite element method (FEM) simulation reveals that both device dimensions and shapes of the suspended graphene membranes can substantially affect gNEMS ESD discharging characteristics. The discovery offers guidelines for design optimization of gNEMS ESD switch structures.

Investigating Graphene gNEMS ESD Switch for Design Optimization