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A self-aligned fabrication process for top-gate amorphous zinc-tin oxide (a-ZTO) thin-film transistors (TFTs) is developed, in which the source/drain (S/D) doping is realized through depositing a thin aluminum (Al) film on S/D regions and performing a thermal annealing. Results indicate that a chemical oxidation-reduction reaction between Al and a-ZTO films takes place during the thermal annealing process, and shallow donors of oxygen vacancies and metal tin (Sn) interstitials are thus generated. The formed S/D regions have a high carrier concentration over 1 &#x00D7;10 <sup>20</sup> cm $^{-3}$ , low sheet resistance of 0.57 k &#x03A9;/sq, and high thermal stability even in oxygen ambient. The fabricated a-ZTO TFTs exhibit excellent electrical performances, including a low channel-width-normalized S/D resistance of about 7.05 &#x03A9; cm, a high field-effect mobility of 15.7 cm<sup>2</sup>/Vs, a high on/off current ratio of over $10 ^{8}$ , and near-zero turn-on voltage. Moreover, good electrical stability with less than 0.2-V threshold voltage shift under &#x00B1;30-V gate bias stresses is also achieved.

Self-Aligned Top-Gate Amorphous Zinc-Tin Oxide Thin-Film Transistor With Source/Drain Regions Doped by Al Reaction