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A novel area-efficient snapback-free silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed and investigated for the first time in this paper. The device features an N+ anode, three separated P+ anodes, and a P-buried layer (PBL) in the N-buffer of the anode region. The N-buffer between all these components above forms a 3-D L-shaped extraction path. The L-shaped extraction path not only makes the device area-efficient but also increases the anode distributed resistance (<inline-formula> <tex-math notation="LaTeX">${R} _{\mathrm{ SA}}$ </tex-math></inline-formula>). Therefore, the snapback effect could be suppressed, and the tradeoff between the on-state voltage (<inline-formula> <tex-math notation="LaTeX">${V} _{\mathrm{ on}}$ </tex-math></inline-formula>) and turn-off energy (<inline-formula> <tex-math notation="LaTeX">${E} _{\mathrm{ off}}$ </tex-math></inline-formula>) is improved effectively. Simulation results show that the proposed device eliminates the snapback effect with 63% and 77% reduction of the anode region area compared with the segmented trenches in the anode region (STA) LIGBT and the separated shorted anode (SSA) LIGBT, respectively. At the same <inline-formula> <tex-math notation="LaTeX">${V} _{\mathrm{ on}}$ </tex-math></inline-formula>, the LEP LIGBT reduces the turn-off time (<inline-formula> <tex-math notation="LaTeX">${t} _{\mathrm{ off}}$ </tex-math></inline-formula>) and <inline-formula> <tex-math notation="LaTeX">${E} _{\mathrm{ off}}$ </tex-math></inline-formula> by 40% and 28%, respectively, compared with the STA LIGBT. Moreover, at the same <inline-formula> <tex-math notation="LaTeX">${E} _{\mathrm{ off}}$ </tex-math></inline-formula>, the LEP LIGBT reduces <inline-formula> <tex-math notation="LaTeX">${V} _{\mathrm{ on}}$ </tex-math></inline-formula> by 17%, compared with the SSA LIGBT.

Area-Efficient and Snapback-Free SOI LIGBT With L-Shaped Extraction Path