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In this paper, for the first time, the performance analysis of short channel In0.53Ga0.47As quantum well (QW) 3-D tri-gate technology with advanced high-&#x03BA; gate dielectric, TaSiOx is presented. We benchmark the projected performance of sub-10 nm In0.53Ga0.47As transistor technology as a function of fin width, fin aspect ratio, and gate length scaling based on present-day lithographic advancement aiding InGaAs QW tri-gate technology as a replacement to Si for sub-10 nm transistor technology. The highly scaled oxide (EOT ~ 12A&#x030A;) while retaining superior interfacial properties (Dit ~ 4 &#x00D7; 1011 cm-2eV-1) provides higher ON current for given idle performance. Furthermore, the simulated In0.53Ga0.47As tri-gate transistor exhibits superior gate electrostatic control with low OFF-state current (IOFF) ~ 24.5 nA/&#x03BC;m, peak transconductance (gm) ~ 2 mS/ &#x03BC;m and high ION/IOFF ratio~ 2.3 &#x00D7; 103, aiding the case of alternate channel transistors for high-speed and low-power CMOS logic.

Performance Analysis of TaSiOx Inspired Sub-10 nm Energy Efficient In0.53Ga0.47As Quantum Well Tri-Gate Technology

Performance Analysis of TaSiO_x Inspired Sub-10 nm Energy Efficient In_0.53Ga_0.47As Quantum Well Tri-Gate Technology