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As the one-chip integration of HW modules designed by different companies becomes more and more popular, reliability of a HW design and evaluation of the timing behavior during the prototype stage are absolutely necessary. One way to guarantee reliability is the use of robust design styles, e.g., delay insensitivity. For early timing evaluation, two aspects must be considered: a) the timing needs to be proportional to technology variations, and b) the implemented architecture should be identical for prototype and target. The first can be met also by delay insensitive implementation. The latter one is the key point. A unified architecture is needed for prototyping as well as implementation. Our new approach to rapid prototyping of signal processing tasks is based on a configurable, delay insensitive implemented processor called FLYSIG (dataflow oriented delay-insensitive signal processing). In essence, the FLYSIG processor can be understood as a complex FPGA where the CLBs are substituted by bit serial operators. The general concept is detailed and first experimental results are given for demonstration of the main advantages: delay insensitive design style, direct correspondence between prototyping and target architecture, high performance and reasonable shortening of the design cycle.

FLYSIG: dataflow oriented delay-insensitive processor for rapid prototyping of signal processing