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IDDQ or steady state current testing has been extensively used in the industry as a mainstream defect detection and reliability screen. The background leakage current has increased significantly with the advent of ultra deep submicron technologies. The increased background leakage makes it difficult to use single threshold IDDQ testing to differentiate defect-free chips from those with defects that draw small amount of currents. Several techniques that improve the resolution of IDDQ testing have been proposed to replace the single threshold detection scheme. However, even these techniques are challenged to detect defects in the presence of leakage currents in excess of a few mA. All of these techniques use a single IDDQ measurement per circuit configuration for detection and thus the scalability of these techniques is limited. Quiescent Signal Analysis (QSA) is a novel IDDQ defect detection and diagnosis technique that uses IDDQ measurements at multiple chip supply pads. Implicit in our methodology is a leakage calibration technique that scales the total leakage current over multiple simultaneous measurements. This helps in decreasing the background leakage component in individual measurements and thus increases the resolution of this technique to subtle defects. The effectiveness of this technique is demonstrated in this paper using simulation experiments on portion of a production power grid. Predicted chip size and leakage values from the International Technology Roadmap for semiconductors (ITRS) are used in these experiments. The performance of the proposed technique is evaluated using three different intra-die process variation distribution models.

Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement