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Parallel and monolithic 3D-integration directions offer pathways to realize 3D integrated circuits but still lead to layer-by-layer implementations. This mindset causes challenging connectivity and alignment between layers when connected in 3D, with a routing access that can be even worse than 2D-CMOS, which fundamentally limits their potential. To fully exploit the opportunities in the third dimension, we propose Skybridge-3D-CMOS (S3DC), a fine-grained 3D-integration approach that is directly composed in 3D, utilizing the vertical dimension vs. a layer-by-layer assembly mindset. S3DC uses a novel wafer fabric creation with direct 3D design and connectivity in the vertical dimension. It builds on a uniform vertical nanowire template that is processed as a single wafer, it incorporates specifically architected structures for realizing devices, circuits, and heat management in 3D. Novel 3D interconnect concepts, including within the silicon layers, enable significantly improved routing flexibility in three dimensions and a high-density 3D design paradigm overall. Intrinsic components for fabric-level heat management are introduced. Extensive bottom-up simulations and experiments have been presented to validate the key fabric-enabling concepts. Evaluations indicate up to 40x density and 10x performance-per-watt benefits against 16-nm 2D-CMOS for the circuits studied, benefits are also substantially beyond what was projected in other 3D directions.

Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology