English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools annual

Global: Zendy Free Plan

Global: Zendy Tools monthly

Global: Zendy Plus monthly

In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A current-starved voltage controlled oscillator (VCO) is treated as a case study and to the best of the authors' knowledge, this is the first VCO design that accounts for both parasitic degradation and process variation together. The physical design of the VCO is carried out in a generic 90 nm Salicide 1.2 V / 2.5 V 1 Poly 9 Metal process design kit. The oscillation frequency is the objective function with the area overhead as constraint. A performance degradation of 43.5 % is observed when the parasitic extracted circuit was subjected to worst case process variation. After a single physical design iteration, the frequency of oscillation was within 4.5 % of the target.

Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design