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Phase-locked loops (PLL), Costas loops and other synchronizing circuits are featured by the presence of a nonlinear phase detector, described by a periodic nonlinearity. In general, nonlinearities can cause complex behavior of the system such as multi-stability and chaos. Even if the phase locking is guaranteed for any initial conditions, the transient behavior of the circuit can still be unsatisfactory due to the cycle slipping. Growth of the phase error caused by cycle slipping is undesirable, leading e.g. to demodulation and decoding errors. This makes the problem of estimating the phase error oscillations and number of slipped cycles in nonlinear PLL-based circuits extremely important for modern telecommunications. Most mathematical results in this direction, available in the literature, focus on the phase jitter and cycle slipping under random noise and examine the relations between the probabilistic characteristics of the noise and of the phase error, e.g. the expected number of slipped cycles. At the same time, cycle slipping occurs also in deterministic systems with periodic nonlinearities, depending on the initial conditions, properties of the linear part and the periodic nonlinearity and other factors such as delays in the loop. In the present paper we give analytic estimates for the number of slipped cycles in PLL-based systems, governed by integro-differential equations, allowing to capture effects of high-order dynamics, discrete and distributed delays. We also consider the effects of singular small-parameter perturbations on the cycle slipping behavior.

Cycle slipping in nonlinear circuits under periodic nonlinearities and time delays