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Under modern VLSI technology, process variations greatly affectcircuit performance, especially clock skew which is very timingsensitive. Unwanted skew due to process variation forms a bottleneckpreventing further improvement on clock frequency. Impactfrom intra-chip interconnect variation is becoming remarkable andis difficult to be modeled efficiently due to its distributive nature.Through wire shaping analysis, we establish an analytical boundfor the unwanted skew due to wire width variation which is thedominating factor among interconnect variations. Experimental resultson benchmark circuits show that this bound is safer, tighterand computationally faster than similar existing approach.

Analytical bound for unwanted clock skew due to wire width variation