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ATPG tools generate test vectors assuming zero delay model forlogic gates.In reality, however, gates have finite rise and falldelays that are dependent on process, voltage, and temperaturevariations across different dies on a wafer and within a die.A testengineer must verify the vectors for timing correctness before theyare handed off to the product engineer.Currently, validation oftests is done using dynamic simulation of the circuit using the testvectors.A test vector is invalidated if it cannot reliably distinguishbetween a good and a faulty circuit under the signal placement andobservation error window of the tester equipment.Since structuraltests can result in much more switching activity in the circuit thanwhat is estimated during normal functioning, the IR drop in thepower & ground lines can be significant, adversely impacting pathdelays.As a result, the validation performed by simulation can beerror prone.Oversizing the power rails to address this problemimpacts the yield.We therefore propose the verification of testvectors for IR drop failure and present a flow for identifyingfailing vectors.Attempting to address this verification in dynamicsimulation will force the use of circuit simulation or mixed-levelsimulation techniques, which are expensive in terms of run time.We discuss a static approach to validate the test vectors for failurein the presence of IR drop problems.

Static Verification of Test Vectors for IR Drop Failure