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In this work, we present a new structure for multiplication in finite fields. This structure is based on a digit-level LFSR (Linear Feedback Shift Register) multiplier, in which the area of the digit-multipliers is reduced using the Karatsuba method. We compare our results with the other works of the literature for F<inf>397</inf>. Furthermore, we propose new formulas for multiplication in F<inf>36.97</inf>. These new formulas reduce the number of F<inf>397</inf>-multiplications from 18 to 15. The finite fields F<inf>397</inf> and F<inf>36.97</inf> are important fields for pairing based cryptography.

Efficient FPGA-Based Multipliers for F397 and F36.97