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The embedded DRAM (eDRAM) is more and more used in system-on-chip (SOC). It is challenging to integrate the DRAM capacitor process into a logic process to get satisfactory yields. The specific process of DRAM capacitor and the low capacitance value (/spl sim/30 fF) of this device induce problems of process monitoring and failure analysis. We propose a new test structure to measure the capacitance value of each DRAM cell capacitor in a DRAM array. This concept has been validated by simulation on a 0.18 /spl mu/m eDRAM technology.

A new embedded measurement structure for eDRAM capacitor